|MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture|
|Prev||Chapter 5. Detailed Requirements||Next|
Addr Mode Mnemonic Format/Opcode 8 4 4 ----------------------- S BEX N | 77 | 0000 | N | -----------------------
Description. This instruction provides a means to jump to a routine in another address state, AS. It is typically used to make controlled, protected calls to an executive. The 4-bit literal N selects one of 16 executive entry points to be used. Execution of this instruction causes an interrupt to occur using the EXEC call interrupt vector (interrupt 5). The new IC is loaded from the Nth location following the SW in the new processor state. The linkage pointer (LP), service pointer (SVP), and the new processor state (new MK, new SW, and new IC) are fetched from address state zero. The current processor state (old MK, old SW, and old IC) are stored in the address state specified by the new SW AS field. Interrupts are disabled when BEX is executed. The EXEC call interrupt cannot be masked or disabled. Arguments associated with the BEX instruction are passed by software convention. The processor lock and key function is ignored when this instruction is executed. An attempt to branch into an execute protected area of memory shall result in FT being set to 1.
Register Transfer Description.
(RQ,RQ+1,RQ+2) <-- (MK,SW,IC);
(SVP) <-- [2B16], where AS = 0;
(MK,SW,IC) <-- [(SVP),(SVP)+1,(SVP)+2+N)], where AS = 0;
(LP) <-- [2A16], where AS = 0;
[(LP),(LP)+1,(LP)+2] <-- (RQ,RQ+1,RQ+2), where AS = SW 12-15;
Registers Affected. MK, SW, IC, PI