4.6. Interrupt Control

4.6.1. Interrupts

The instruction set shall support a minimum of sixteen (16) interrupts as shown in Table VIII. An interrupt request may occur at any time; however, the interrupt processing must wait until the current instruction is completed. An exception to this is the Move Multiple Word which may be interrupted after each single word transfer. The overall procedure for acceptance of, responding to, and processing of an interrupt shall be as illustrated by the flow chart of Figure 2. Interrupt Acceptance

The interrupt system shall have the capability to accept external and internal interrupts. Figure 2 indicates the relationship between the interrupt signals, the pending interrupt register, the interrupt signals and the fundamental communications between the interrupt system and the CPU. Interrupt Software Control

Software shall be able to input from or output to the interrupt mask register as well as the pending interrupt register. Also, software shall be able to disallow recognition of interrupts via the "disable interrupts" signal (without inhibiting interrupt acceptance into the pending interrupt register) and to allow recognition of interrupts via the "enable interrupts" signal. The disabling shall not allow any interrupt after the beginning of the disable instruction. The CPU's interrupt service hardware shall continue to "disable interrupts" for one instruction after the Enable Interrupts instruction has completed. Full descriptions of the interrupt instructions are given in the input/output instruction repertoire.

Table VIII. Interrupt Definitions

Interrupt Number Interrupt Mask Bit Number Interrupt Linkage Pointer Address (Hex) Interrupt Service Pointer Address (Hex)  
0 0 20 21 Power Down (cannot be masked or disabled)
1 1 22 23 Machine Error (cannot be disabled)
2 2 24 25 Spare
3 3 26 27 Floating Point Overflow
4 4 28 29 Fixed Point Overflow
5 5 2A 2B Executive Call (cannot be masked or disabled)
6 6 2C 2D Floating Point Underflow
7 7 2E 2F Timer A (if implemented)
8 8 30 31 Spare
9 9 32 33 Timer B (if implemented)
10 10 34 35 Spare
11 11 36 37 Spare
12 12 38 39 Input/Output Level 1 (if implemented)
13 13 3A 3B Spare
14 14 3C 3D Input/Output Level 2 (if implemented)
15 15 3E 3F Spare

Note: Interrupt number 0 has the highest priority. Priority decreases with increasing interrupt number.

Figure 2. Interrupt System Flowchart Interrupt Priority Definitions

The priority definitions of the interrupts and their required relationship to the interrupt mask and interrupt pointer addresses are illustrated in Table VIII, Interrupt Definitions. The power down interrupt shall initiate the power down sequence and cannot be masked or disabled during normal operation of the computer. The executive call interrupt, used with the Branch to Executive instruction, BEX, (see Section 5.30) also cannot be masked or disabled. The machine error interrupt cannot be disabled but can be masked during normal operation of the computer. All other interrupts can be disabled and masked. If a floating point overflow/underflow or fixed point overflow condition occurs, then the instruction generating that condition shall be interrupted at its completion if the interrupt is unmasked and enabled. Interrupt Vectoring Mechanism

The vectoring mechanism shall be as illustrated on Figure 3. For each interrupt there shall be two fixed memory locations in the "vector table": (1) the first memory location (Linkage Pointer) shall be defined as the address of where to store the current (old) state of the computer (i.e., "old interrupt mask","old status word", and "old instruction counter"); and (2) the second memory location (Service Pointer) shall be defined as the address of the next (new) state of the computer (i.e., "new interrupt mask", "new status word", and "new instruction counter"). Returning from interrupts may be accomplished by executing the Load Status (LST/LSTI) instruction with the value/address of the Linkage Pointer for an address field.

Figure 3. Interrupt Vectoring System